This invention relates generally to programmable memory storage devices. More particularly, the invention relates to a one-time programmable storage device with vertically oriented fuse or with fuse and anti-fuse combination unit memory cells.
The demand for semiconductor devices has increased dramatically in recent years as evidenced by the pervasiveness of consumer electronic devices. Most or all consumer electronics are possible because of developments in semiconductor devices. As the electronic devices become smaller, more sophisticated, and less expensive, the demand for highly dense semiconductor devices at a lower cost is increasing.
In the field of memories, the demand for ever increasing densities and lower cost is particularly true, especially for non-volatile memories, i.e., those memories that do not lose data even when power is not supplied.
A non-volatile memory may be a one-time programmable (xe2x80x9cOTPxe2x80x9d) or re-programmable. As the name suggests, OTP memory is programmed once, and it is permanent for all practical purposes. Most OTP memories can be categorized into four basic types: 1) anti-fuse, 2) fuse, 3) charge storage (EPROM), and 4) mask ROM.
Programmable elements based on an anti-fuse typically rely on breakdown of metal-insulator-metal or diode structures to create the two resistance states. Programming voltages in excess of 10 V are generally required. In addition, the current required for anti-fuse breakdown can be large, which leads to large drive transistors. If used as a memory cell, an access transistor is typically included in the memory cell.
Memory cells based on a fuse storage element are not widely used due to the large cell size. A planar fuse requires a minimum area of 8xcex2 (where xcex is the minimum photolithographic feature size), since a contact region is needed on each end of the fuse. Generally the fuse is even larger than 8xcex2 to provide a more readily programmed element. As for the anti-fuse, the programming current can be large, which leads to large drive transistors as mentioned above. Adding an access transistor increases the minimum cell size even further.
In the case of EPROM, programming the bit requires a high write voltage to transfer charge from the substrate to the floating gate of the memory cell by Fowler-Nordheim electron tunneling. Write speed is limited by the tunneling current density. EPROM is unique within the OTP memory family in that it can be reprogrammed, but it has to be erased first by exposing the memory array to a ultra-violet light source. This procedure is not easily implemented and the entire memory is erased.
A mask read only memory (xe2x80x9cmask ROMxe2x80x9d) is a memory that is programmed at the time of fabrication, and thus is a type of an OTP memory. A mask ROM is relatively simpler since the circuit to enable writing is not needed, and thus is less costly when compared to other OTP memories. Because the programming is part of the fabrication process, the mask ROM cannot be xe2x80x9cfield programmedxe2x80x9d, i.e., programmed by the purchaser to fit the particular needs of the purchaser. In other words, mask ROMs do not provide the flexibility of field programmability. Also, unless the mask ROMs are manufactured in bulk, cost savings cannot generally be realized.
Existing OTP memory technologies described above are based on cell sizes considerably larger than 4xcex2, the minimum cell size for a cross-point memory. In addition, in each case the memory cell consists of a single plane of memory elements constructed on a single crystal silicon substrate, with the sense and programming electronics located around the periphery of the memory array. Consequently, high density, low cost OTP memories are difficult to fabricate.
In accordance with an aspect of the invention, a one-time programmable (xe2x80x9cOTPxe2x80x9d) memory may include one or more memory arrays. Each memory array may include one or more row conductors extending in a row direction and one or more column conductors extending in a column direction such that a cross-point is formed at intersections between the row and column conductors. The memory array may also include a state element formed in at least one cross-point. The state element may include a fuse and may additionally include an anti-fuse in series with the fuse. The state element is in electrical contact with the row and column conductors.
In accordance with another aspect of the principles of the invention, a method of programming an OTP memory may include the steps of selecting a state element, applying a writing voltage VWR to a row conductor electrically connected to the selected state element, and grounding a column conductor electrically connected to the selected state element. By applying voltage VWR to the row conductor and grounding the column conductor, a critical voltage drop VC occurs through the selected state element causing the state element to change states.
In accordance with yet another aspect of the principles of the invention, a method of reading an OTP memory may include the steps of selecting a state element, applying a reading voltage VRD to a row conductor electrically connected to the selected state element, and sensing an amount of current from a column conductor electrically connected to the selected state element. Sensing a relatively high current indicates that the state element is in a first state (a low resistance state) and sensing a relatively low current indicates that the state element is in a second state (a high resistance state).
Certain advantages follow from certain embodiments of the invention. For example, the size of individual unit memory cell is dramatically reduced. This enables providing a high density OTP memory cell at much lower cost. Also, the unit memory cells may be fabricated using standard semiconductor processes and materials, and thus, little to no capital investment is required beyond that present in the current state-of-the-art manufacturing. Further, the current flow in the memory cells is substantially perpendicular (vertical) to the substrate plane. This allows the cells to be inserted between adjacent conductors. In particular, the cells can be placed at an intersection of a cross-point array of conductors to form a cross-point OTP memory array. The cross-point memory arrays can be fabricated such that the planar area of each memory cell is 4xcex2. Planes of these arrays can be stacked on top of one another, which increases the density dramatically.